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CAT24C32 32-Kb I2C CMOS Serial EEPROM
Description
The CAT24C32 is a 32-Kb CMOS Serial EEPROM devices, internally organized as 128 pages of 32 bytes each. It features a 32-byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. External address pins make it possible to address up to eight CAT24C32 devices on the same bus.
Features
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Supports Standard, Fast and Fast-Plus I2C Protocol 1.7 V to 5.5 V Supply Voltage Range 32-Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range PDIP, SOIC, TSSOP, TDFN and UDFN 8-lead Packages This Device is Pb-Free, Halogen Free/BFR Free, and RoHS Compliant
VCC
SOIC-8 W SUFFIX CASE 751BD
UDFN-8 HU4 SUFFIX CASE 517AZ
TDFN-8 VP2 SUFFIX CASE 511AK
PDIP-8 L SUFFIX CASE 646AA
TSSOP-8 Y SUFFIX CASE 948AL
UDFN-8 HU3 SUFFIX CASE 517AX
PIN CONFIGURATION
A0 A1 A2 VSS 1 VCC WP SCL SDA
PDIP (L), SOIC (W), TSSOP (Y), TDFN (VP2), UDFN (HU3, HU4) SCL CAT24C32 SDA For the location of Pin 1, please consult the corresponding package drawing.
A2, A1, A0 WP
PIN FUNCTION
Pin Name VSS A0, A1, A2 SDA SCL WP VCC VSS Function Device Address Serial Data Serial Clock Write Protect Power Supply Ground
Figure 1. Functional Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2010
July, 2010 - Rev. 12
1
Publication Order Number: CAT24C32/D
CAT24C32
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Storage Temperature Voltage on any Pin with Respect to Ground (Note 1) Ratings -65 to +150 -0.5 to +6.5 Units C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol NEND (Note 3) TDR Endurance Data Retention Parameter Min 1,000,000 100 Units Program/Erase Cycles Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = -40C to +125C and VCC = 1.7 V to 5.5 V, TA = -20C to +85C, unless otherwise specified.)
Symbol ICCR ICCW ISB Parameter Read Current Write Current Standby Current Test Conditions Read, fSCL = 400 kHz Write, fSCL = 400 kHz All I/O Pins at GND or VCC TA = -40C to +85C VCC 3.3 V TA = -40C to +85C VCC > 3.3 V TA = -40C to +125C IL VIL VIH VOL1 VOL2 I/O Pin Leakage Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage VCC < 2.5 V, IOL = 3.0 mA VCC < 2.5 V, IOL = 1.0 mA Pin at GND or VCC -0.5 VCC x 0.7 Min Max 1 2 1 3 5 2 VCC x 0.3 VCC + 0.5 0.4 0.2 mA V V V V Units mA mA mA
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = -40C to +125C and VCC = 1.7 V to 5.5 V, TA = -20C to +85C, unless otherwise specified.) Symbol CIN (Note 4) CIN (Note 4) IWP (Note 5) Parameter SDA I/O Pin Capacitance Input Capacitance (other pins) WP Input Current Conditions VIN = 0 V, TA = 25C, f = 1.0 MHz VIN = 0 V, TA = 25C, f = 1.0 MHz VIN < VIH, VCC = 5.5 V VIN < VIH, VCC = 3.3 V VIN < VIH, VCC = 1.8 V VIN < VIH Max 8 6 130 120 80 2 Units pF pF mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. 5. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
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CAT24C32
Table 5. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = -40C to +125C and VCC = 1.7 V to 5.5 V, TA = -40C to +85C.) (Note 6) Standard VCC = 1.7 V - 5.5 V Symbol FSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR (Note 7) tF (Note 7) tSU:STO tBUF tAA tDH Ti (Note 7) tSU:WP tHD:WP tWR tPU (Notes 7, 8) 6. 7. 8. 9. Parameter Clock Frequency START Condition Hold Time Low Period of SCL Clock High Period of SCL Clock START Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Condition Setup Time Bus Free Time Between STOP and START SCL Low to Data Out Valid Data Out Hold Time Noise Pulse Filtered at SCL and SDA Inputs WP Setup Time WP Hold Time Write Cycle Time Power-up to Ready Mode 0 2.5 5 1 100 100 0 2.5 5 1 0.1 4 4.7 3.5 100 100 0 1 5 1 4 4.7 4 4.7 0 250 1,000 300 0.6 1.3 0.9 50 100 Min Max 100 0.6 1.3 0.6 0.6 0 100 300 300 0.25 0.5 0.40 Fast VCC = 1.7 V - 5.5 V Min Max 400 0.25 0.45 0.40 0.25 0 50 100 100 Fast-Plus (Note 9) VCC = 2.5 V - 5.5 V TA = -405C to +855C Min Max 1,000 Units kHz ms ms ms ms ms ns ns ns ms ms ms ns ns ms ms ms ms
Test conditions according to "A.C. Test Conditions" table. Tested initially and after a design or process change that affects this parameter. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Fast-Plus (1 MHz) speed class available for product revision "F". The die revision "F" is identified by letter "F" or a dedicated marking code on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels Input Rise and Fall Time Input Reference Levels Output Reference Level Output Test Load 0.2 x VCC to 0.8 x VCC 50 ns 0.3 x VCC, 0.7 x VCC 0.5 x VCC Current Source IOL = 3 mA (VCC 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT24C32
Power-On Reset (POR) Each CAT24C32 incorporates Power-On Reset (POR) circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This bi-directional POR behavior protects the device against `brown-out' failure following a temporary loss of power. Pin Description SCL: The Serial Clock input pin accepts the clock signal generated by the Master. SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally. WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally. Functional Description The CAT24C32 supports the Inter-Integrated Circuit (I2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CAT24C32 operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles. The 2-wire I2C bus consists of two lines, SCL and SDA, connected to the VCC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A `0' is transmitted by pulling a line LOW and a `1' by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH.
START/STOP Condition I2C Bus Protocol
An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CAT24C32, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A2, A1 and A0, must match the logic state of the similarly named input pins. The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3). During the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5.
Acknowledge
SCL
SDA START CONDITION STOP CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 3. Slave Address Bits
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CAT24C32
BUS RELEASE DELAY (TRANSMITTER) SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER 1 8 9 BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT FROM RECEIVER START ACK DELAY ( tAA) ACK SETUP ( tSU:DAT)
Figure 4. Acknowledge Timing
tF tLOW SCL tSU:STA SDA IN tAA SDA OUT tHD:SDA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
tDH
tBUF
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write Acknowledge Polling
To write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to `0'. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (tWR), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 7).
Page Write
As soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (tWR) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK.
Hardware Write Protection
The Byte Write operation can be expanded to Page Write, by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (tWR).
With the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 9). If the WP pin is HIGH during the strobe interval, the Slave will not acknowledge the data byte and the Write request will be rejected.
Delivery State
The CAT24C32 is shipped erased, i.e., all bytes are FFh.
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CAT24C32
BUS ACTIVITY: S T A MASTER R T S SLAVE *a15 - a12 are don't care bits A C K ADDRESS BYTE a15 - a8 **** A C K A C K A C K ADDRESS BYTE a7 - a0 DATA BYTE d7 - d0 S T O P P
SLAVE ADDRESS
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit Byte n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 7. Write Cycle Timing
BUS ACTIVITY: S T A MASTER R T S SLAVE
SLAVE ADDRESS
ADDRESS BYTE
ADDRESS BYTE
DATA BYTE n
DATA BYTE n+1
DATA BYTE n+P
S T O P P
n=1 P 31
A C K
A C K
A C K
A C K
A C K
A C K
A C K
Figure 8. Page Write Sequence
ADDRESS BYTE 1 SCL 8 9 1
DATA BYTE 8
SDA
a7
a0 tSU:WP
d7
d0
WP tHD:WP
Figure 9. WP Timing
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CAT24C32
READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to `1'. The Slave responds with ACK and starts shifting out data residing at the current address. After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode.
Selective Read
Write sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to `1'. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11).
Sequential Read
To read data residing at a specific address, the selected address must first be loaded into the internal address register. This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to `0' and then sends two address bytes to the Slave. Rather than completing the Byte
BUS ACTIVITY MASTER S T A R T S SLAVE
If, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory.
N O
SLAVE ADDRESS
S AT CO KP P
A C K 9
DATA BYTE
SCL
8
SDA
8th Bit DATA OUT NO ACK STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY: S T A MASTER R T S SLAVE A C K A C K A C K S T A R T S A C K DATA BYTE N O A C K
SLAVE ADDRESS
ADDRESS BYTE
ADDRESS BYTE
SLAVE ADDRESS
S T O P P
Figure 11. Selective Read Sequence
BUS ACTIVITY: MASTER SLAVE ADDRESS A C K A C K A C K N O A C K
S T O P P
SLAVE
A C K
DATA BYTE n
DATA BYTE n+1
DATA BYTE n+2
DATA BYTE n+x
Figure 12. Sequential Read Sequence
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CAT24C32
PACKAGE DIMENSIONS
PDIP-8, 300 mils CASE 646AA-01 ISSUE A
SYMBOL A A1 A2 b E1 b2 c D E E1 e eB PIN # 1 IDENTIFICATION D L 7.87 2.92 3.30 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 BSC 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25 7.11 MIN NOM MAX 5.33
TOP VIEW E
A
A2
A1 b2 L c
e SIDE VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001.
b
eB
END VIEW
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CAT24C32
PACKAGE DIMENSIONS
SOIC 8, 150 mils CASE 751BD-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e h L PIN # 1 IDENTIFICATION TOP VIEW 0.25 0.40 MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00
0
8
D
h
A1
A
c e SIDE VIEW b L END VIEW
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
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CAT24C32
PACKAGE DIMENSIONS
TSSOP8, 4.4x3 CASE 948AL-01 ISSUE O
b
SYMBOL
A A1 A2 b E1 E c D E E1 e L L1
MIN
0.05 0.80 0.19 0.09 2.90 6.30 4.30
NOM
MAX
1.20 0.15
0.90
1.05 0.30 0.20
3.00 6.40 4.40 0.65 BSC 1.00 REF
3.10 6.50 4.50
0.50
0.60
0.75
e
0
8
TOP VIEW D
A2
A
q1
c
A1 SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153.
L1 END VIEW
L
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CAT24C32
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD CASE 517AZ-01 ISSUE O
D A b e L
DAP SIZE 1.8 x 1.8 E2
E
PIN #1 IDENTIFICATION
A1 PIN #1 INDEX AREA TOP VIEW SIDE VIEW D2 BOTTOM VIEW
SYMBOL A A1 A3 b D D2 E E2 e L
MIN 0.45 0.00 0.20 1.95 1.35 2.95 1.25 0.25
NOM 0.50 0.02 0.127 REF 0.25 2.00 1.40 3.00 1.30 0.50 REF 0.30
MAX 0.55 0.05 0.30 2.05 1.45 3.05 1.35 0.35 A3 0.0 - 0.05 DETAIL A 0.065 REF Copper Exposed DETAIL A FRONT VIEW A3 A
0.065 REF
Notes: (1) All dimensions are in millimeters. (2) Refer JEDEC MO-236/MO-252.
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CAT24C32
PACKAGE DIMENSIONS
TDFN8, 2x3 CASE 511AK-01 ISSUE A
D A e b
E
E2 PIN#1 IDENTIFICATION
A1 PIN#1 INDEX AREA D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 0.50 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40 FRONT VIEW A2 A3
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
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CAT24C32
PACKAGE DIMENSIONS
UDFN8, 2x3 CASE 517AX-01 ISSUE O
D A DETAIL A
DAP SIZE 1.3 x 1.8
E PIN #1 IDENTIFICATION
E2
A1 PIN #1 INDEX AREA TOP VIEW SIDE VIEW D2 BOTTOM VIEW
SYMBOL A A1 A3 b D D2 E E2 e K L
MIN 0.45 0.00 0.20 1.90 1.50 2.90 0.10
NOM 0.50 0.02 0.127 REF 0.25 2.00 1.60 3.00 0.20 0.50 TYP 0.10 REF
MAX 0.55 0.05 K 0.30 2.10 1.70 3.10 0.30 e
b
L
DETAIL A
A3 0.40 A
0.30
0.35
Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229.
A1 FRONT VIEW
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CAT24C32
Example of Ordering Information
Prefix CAT Device # 24C32 Suffix Y I -G T3
Company ID Product Number 24C32
Temperature Range I = Industrial (-40C to +85C) E = Extended (-40C to +125C)
Lead Finish G: NiPdAu
Tape & Reel (Note 15) T: Tape & Reel 2: 2,000 / Reel (Note 14) 3: 3,000 / Reel
Package L: PDIP W: SOIC, JEDEC Y: TSSOP HU4: UDFN (2 x 3 mm) VP2: TDFN (2 x 3 mm) (Note 14) HU3: UDFN (2 x 3 mm) (Note 14) 10. All packages are RoHS-compliant (Lead-free, Halogen-free). 11. The standard lead finish is NiPdAu. 12. The device used in the above example is a CAT24C32YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel, 3,000/Reel). 13. For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 14. The TDFN 2 x 3 x 0.75 mm (VP2) and UDFN 2 x 3 x 0.5 mm (HU3) are not recommended for new design. Please replace with UDFN 2 x 3 x 0.5 mm, extended pad (HU4). 15. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CAT24C32/D

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